Jual LA76810A.

LA76810A.

LA76810A Overview LA76810A is a VIF/SIF/Y/Deflection 1chip IC for PAL/NTSC color television sets. Functions • VIF/SIF/Y/Deflection Implemented in a 1chip. • I2 C Bus Control Specifications Maximum Ratings at Ta = 25°C


■ Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications.
■ SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein

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Jual L292

L292

SWITCH-MODE DRIVER FOR DC MOTORS

*DRIVING CAPABILITY : 2 A, 36 V, 30 KHz 2
*LOGIC CHIP ENABLE
*EXTERNAL LOOP GAIN ADJUSTEMENT
*SINGLE POWER SUPPLY (18 TO 36 V)
*INPUT SIGNAL SYMMETRIC TO GROUND
*THERMAL PROTECTION

DESCRIPTION
The L292 is a monolithic LSI circuit in 15-lead Multiwatt ® package. It is intended for use, together with L290 and L291, as a complete 3-chip motor positioning system for applications such as carriage/daisy-wheel position control in type-writes. The L290/1/2 system can be directly controlled by

SYSTEM DESCRIPTION

The L290, L291 and L292 are intended to be used as a 3-chip microprocessor controlled positioning system. The device may be used separately - particularly the L292 motor driver - but since they will usually be used together, a description of a typical L290/1/2 system follows. Figure 1. System Block Diagram The system operates in two modes to achieve high speed, high-accurancy positioning. Speed commands for the system originate in the microprocessor. It is continuosly updated on the motor position by means of pulses from the L290 tachometer chip, whitch in tur gets its information from the optical encoder. From this basic input, the microprocessor computes a 5-bit control word that sets the system speed dependent on the distance to travel. When the motor is stopped and the microprocessor orders it to a new positio, the system operates initially in an open-loop configuration as there is no feedback from the tachometer generator. A maximum speed is reached, the tachometer chip output backs off the processor signal thus reducing accelering torque. The motor continues to run at rop speed but under closed-loop control. As the target position is approached, the microprocessor lowers the value of the speed-demand word; this reduces the voltage at the main summing point, in effect braking the motor. The braking is applied progressively until the motor is running at minimum speed. At the time, the microprocessor orders a switch to the position mode, (strobe signal at pin 8 of L291) and within 3 to 4 ms the L292 drives the motor to a null position, where it is held by electronic "detenting". The mechanical/electrical interface consists of an

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AP4435GM

AP4435GM

P-CHANNEL ENHANCEMENT MODE
POWER MOSFET

▼ Simple Drive Requirement
▼ Low On-resistance
▼ Fast Switching Characteristic




Description
Advanced Power MOSFETs from APEC provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness.
The SO-8 package is widely preferred for all commercial-industrial surface mount applications and suited for low voltage applications
such as DC/DC converters.

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CH451S

Features 

■ High Performance 
• fMAX = 400MHz maximum operating frequency
• tPD = 2.5ns propagation delay
• Up to four global clock pins with programmable clock polarity control
• Up to 80 PTs per output

 ■ Ease of Design 
• Enhanced macrocells with individual clock, reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Fast path, SpeedLockingTM Path, and wide-PT path
• Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders

■ Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C) 
• Typical static current 10µA (4032Z)
• Typical static current 1.3mA (4000C)
• 1.8V core low dynamic power
• ispMACH 4000Z operational down to 1.6V VCC

■ Broad Device Offering 
• Multiple temperature range support – Commercial: 0 to 90°C junction (Tj ) – Industrial: -40 to 105°C junction (Tj ) – Extended: -40 to 130°C junction (Tj )
• For AEC-Q100 compliant devices, refer to LA-ispMACH 4000V/Z Automotive Data Sheet
 ■ Easy System Integration
• Superior solution for power sensitive consumer applications
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• Operation with 3.3V (4000V), 2.5V (4000B) or 1.8V (4000C/Z) supplies
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Programmable output slew rate
• 3.3V PCI compatible
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V In-System Programmable (ISP™) using IEEE 1532 compliant interface
• I/O pins with fast setup path
• Lead-free package options

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GM71C18163CT6

GM71C18163CT6

Description 
The GM71C(S)18163C/CL is the new generation dynamic RAM organized 1,048,576 x 16 bit. GM71C(S)18163C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71C(S)18163C/CL offers Extended Data out(EDO) Mode as a high speed access mode. Multiplexed address inputs permit the GM71C(S)18163C/CL to be packaged in standard 400 mil 42pin plastic SOJ, and standard 400mil 44(50)pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment.

Features

* 1,048,576 Words x 16 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time

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79MO5G

79M05/79M12
1 Ampere Surface Mount Negative Three Terminal Voltage Regulators

Features
● Output Voltage: -5 & -12V
● Output current up to 1A
● No external components required
● Internal thermal overload protection
● Internal short-circuit current limiting
● Output transistor safe-area compensation
● Output voltage offered in 4% tolerance

A common ground is required between the input and the output voltages. The input voltage must remain typically 2.0V above the output voltage even during the low point on the Input ripple voltage. XX = these two digits of the type number indicate voltage. * = Cin is required if regulator is located an appreciable distance from power supply filter. ** = Co is not needed for stability; however, it does improve transient response.

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SH6417727F / 6417727F

SH6417727F / 6417727F  TQFP RENESAS

Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series SH7727 HD6417727

Harga : Rp.650.000/pcs
Minimal Order 2 Pcs Indent 1 Minggu


Features

LCD controller (LCDC)
• From 16 x 1 to 1024 x 1024 pixels can be supported
• 4/8/15/16 bpp (bit per pixel) color modes
• 1/2/4/6 bpp (bit per pixel) gray scale
• 8-bit Frame rate controller
• TFT/DSTN/STN
• Signal polarity setting function
• Hardware panel rotation • Power control function
• Selectable clock source (LCLK, bus clock (Bφ), or peripheral clock (Pφ))

AFE I/F
 • ST7550 direct interface
 • Telephone line control
 • 128-word FIFO for transfer
 • 128-word FIFO for receive

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MBM29F800TA-70PFTN Fujitsu

MBM29F800TA-70PFTN  Fujitsu

Harga Rp.95.000/pcc
Minimal Order 5pcs. Indent 1 Minggu

FLASH MEMORY
CMOS 8M (1M × 8/512K × 16) BIT

MBM29F800TA-55/-70/-90/MBM29F800BA-55/-70/-90

■ FEATURES

• Single 5.0 V read, write, and erase Minimizes system     level power requirements
• Compatible with JEDEC-standard commands Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 44-pin SOP (Package suffix: PF)
• Minimum 100,000 write/erase cycles
• High performance 55 ns maximum access time
• Sector erase architecture One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture T = Top sector B = Bottom sector
• Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion
• Low Vcc write inhibit ≤ 3.2 V
 • Erase Suspend/Resume Suspends the erase operation to allow a read data in another sector within the same device
• Hardware RESET pin Resets internal state machine to the read mode
• Sector protection Hardware method disables any combination of sectors from write or erase operations
• Temporary sector unprotection Temporary sector unprotection via the RESET pin.

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